Typically, the active components (e.g., transistors and diodes) and passive components (e.g., capacitors, inductors, resistors) used in circuits for power applications are formed in separated discrete packages. Although passive components, such as capacitors, may be realized on a chip level, the integration of large capacitors is either difficult with power devices (e.g., insulated-gate bipolar transistors) or costly. Currently, there are two ways to integrate capacitors on the same die as a semiconductor device. One approach relies on vertical integration of capacitive structures into the chip die which requires etching deep trenches into the chip die. Larger capacitances require deeper trenches. However, the chip die for power devices should be as thin as possible to achieve low RDSon and favorable thermal behavior. A second approach relies on the lateral integration of capacitive structures into the chip die. This approach however requires forming metal layers over large areas of the chip die which is space-consuming and very costly.